STMicroelectronics (NYSE: STM), one of the world's leading semiconductor companies, today announced it has developed the industry's first 'bridge' chipsets for the proposed iDP (Internal DisplayPort) standard to LVDS (Low-Voltage Differential Signalling) translation for use in next-generation LCD TVs. The new chipsets are compliant with the iDP interface standard recently proposed by ST, in collaboration with LG Display, to the Video Electronics Standards Association (VESA) TV Panel Task Group.

Designed for the connection between the TV-controller SoC (System-on-Chip) and a TV-panel Timing Controller within a TV chassis, iDP is an advanced technology based on DisplayPort, a proven industry-standard technology that is an open and royalty free VESA standard. The new chipsets from ST will be demonstrated for the first time at ST's private suite for customers at CES 2010, January 7-10, in Las Vegas.

Built using DisplayPort technology and featuring low-power design and low EMI (Electro-Magnetic Interference), these new iDP-to-LVDS bridge chipsets from ST will provide robust interoperability and cost effectiveness, enabling customers to quickly validate the new interface standard and enable the deployment of next-generation products with time-to-market advantages.

ST's first iDP-based solution comprises an iDP transmitter and iDP receiver, the STiDP888 and STiDP880, respectively. Together, these form a complete interface translator for high-bandwidth panel-interface applications, redefining and simplifying the panel interface by reducing number of wires, connectors and signal traces, thus driving down the cost of implementation for TV makers.

The chipset solution comprises a single-link iDP interface capable of transporting uncompressed pixel streams up to 12.96Gbps bandwidth between TV SoC and LCD panel module over four pairs of low-cost twisted wires or FFC (Flat Flexible Cable) cabling. ST's iDP transmitter and receiver devices are fully scalable: each chipset can support FHD (Full High-Definition) video (at 1080p/30-bit per pixel) at 120Hz refresh rate; two sets can support FHD-240Hz refresh rate panels.

Both the transmitter and receiver devices integrate high-speed Quad-LVDS interfaces for conversion between conventional Quad-LVDS and iDP to address transitional market needs. These products offer maximum flexibility to TV manufactures and enable seamless transition to iDP.

In addition, the spread-spectrum technique, employed in conjunction with iDP's self clocking, data scrambling and inter-lane de-skewing architecture, bring additional cost savings by eliminating external EMI-reduction components.

The STiDP888 and STiDP880 components are packaged in 164-ball LFBGA package and are available for sampling now.

Further information about iDP Technology

Aimed at implementing the connection between the TV-controller SoC and Timing Controller within the TV chassis, the iDP standard offers highly robust interoperability and cost effectiveness, realized by leveraging the proven DisplayPort technology in its simplest form. With a link operating at 3.24/Gbps per differential pair, only 17 signals (eight differential pairs and one Hot Plug Detect (HPD) signal) are needed to transport Full HD 240Hz at 10 bits per color over the iDP link, substantially fewer than the 96 signals required for a conventional LVDS link. With the dynamic lane-count adjust feature, iDP is capable of supporting pixel rate change due to events such as video frame-rate change and 3D-stereo display timing without visual glitch on a TV screen. The openness of the iDP standard, further enhances cost effectiveness because it solicits competition by many component suppliers without royalty considerations.